Verilog / VHDL Jobs
I have a source code and I want the testbench code for it
Design the control logic for an alarm clock (for simulation purposes 20ns simulation = 1 minute real time –this can be adjusted somewhat for simulation purposes). a) Use multiple input signals (alarm set input, the snooze, and the alarm time). b) The design will contain one output (Alarm_On). A logic high at the output represents the alarm being “on”. c) An input will be used ...
Comparison of CMOS, pseudo NMOS and transmission gate logic in terms of power-delay-area. Using cadence virtuoso using AMI 0.6um or TMSC 0.4um
i want long term employee. if you are expert in verilog, vhdl. please bid here
i want long term employee. if you are expert in verilog, vhdl. please bid here
Want someone who can quickly build an ARINC429 UVM UVC. Very low budget.
about comparison of CMOS, pseudo NMOS and transmission gate logic in term of power delay area
I already have three-phase diode rectifier and I want to make it to three-phase active rectifier on PLECS standalone.
CMOS logic gates, digital circuit design using Verilog HDL and logic synthesis, clock distribution, digital circuit implementations and verification, digital memory and signalling technologies.
Hy, (10 engineers required) I am running a company, i have team of electrical engineers in different domains. Due to heavy work flow i need to extend my team so i need electrical engineers in different domains (electronic, power and communication). I need someone who can work with me for long term. Please bid if you are expert in your field. Please write 786 at the start of your proposal.
More details will be shared via chat
More details will be shared via chat
More details will be shared via chat
Looking for Linux Kernel developers And FPGA developers to port the Mister Project Linux Kernel and U-Boot of DE10 Nano to the Xilinix Ultra96-V2 Zynq UltraScale+ ZU3EG. Once completed we need assistance porting of the existing FPGA cores of Mister Project to the zu3. Mister Project Linux Kernel: [iniciar sesión para ver URL] Mister Project U-Boot: [iniciar sesión para ver URL] ...
You have a VHDL code and you need to describe it. I would provide example
I need the help of someone who could help me propose and implement an algorithm using constraints programming methods that supports formal verification of digital models that can be used on hardware models in VHDL , verilog, e.t.c, its quite urgent please, your help would be highly appreciated
I want 3bit cuonter is tow phases .phase 1 is Dane but I want phase 2 is layout in magic
We need someone to help with some theoretic & programming questions in MPI Parallel C programming, including cost analysis, running time of the program, etc.
Time-to-digital converters based on FPGAs.
Hi, this project will require you to use verilog and basys3 board and logic analyzer to do the work. Contact me if you are an expert in this.
The booth multiplier circuit is from a research paper. I will give you the research paper.
I want someone who has knowledge in Scilab and can write in some codes
design of an FPGA device and its verification
I need an expert who can do implement modular multiplication algorithms in Verilog and simulate their results to make a comparison in their speed of implementation, hardware consumed etc.
I'm required to design this architecture using VHDL. This architecture also consists of hops.
Hello freelancers, I am looking for an expert in VHDL/FPGA for an interesting project. The project is very small and I encourage new freelancers to place the bid. My budget is 30-40 AUD
Hello freelancers, I am looking for an expert in VHDL for an interesting project. The project is very small and I encourage new freelancers to place the bid. My budget is 30-40 AUD
i want long term employee. i need to draw internal block diagram. if you are expert, please bid here
i want long term employee. i need to draw internal block diagram. if you are expert, please bid here
i want long term employee. i need to draw internal block diagram. if you are expert, please bid here
- Develop a micro-threaded RISC-V for low-overhead threading - Integrate with FPGA HLS tool to make a solution of micro-threaded HLS - Need to optimized PPA (Power Performance Area) - Require good problem solving skill - Require good written and oral communication kill
Seeking full-time experienced ASIC Verification Engineers for an ongoing project (12 months+) Essential requirements: Knowledge of at least one industry standard protocol like Ethernet, PCIe, MIPI, USB, AMBA or similar. Ability to update testbench components like reference model/SB, drivers and monitors. Team player with excellent interaction skills. Perl/shell scripting is a good to have. ...