Startup001

I'm Ritika Gharoo. I have been trained on complete PnR flow which includes synthesis to physical verification. I have worked on multiple projects at 28nm using Synopsys flow. one of the projects is a multi-voltage domain project and another project is chip-level implementation.  project flow implemented using design compiler ICC2, PT, Star RC, and IC validator. During this, I have gained exposure to input files, import design, floorplan concept, power planning, placement, SDF generation, ECO closure, and physical verification. plz give me a chance so that i can contribute myself in your project.