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Vhdl LCD finctional

$10-30 USD

Terminado
Publicado hace más de 5 años

$10-30 USD

Pagado a la entrega
In ready projekt on vhdl (tic tac toe game) I need to add state od the gamę on LCD [login to view URL]
ID del proyecto: 17805526

Información sobre el proyecto

4 propuestas
Proyecto remoto
Activo hace 6 años

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$20 USD en 1 día
4,9 (505 comentarios)
8,1
8,1
4 freelancers están ofertando un promedio de $25 USD por este trabajo
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Dear customer, I am really happy to help you out of this project. I would like to introduce that I am an freelancer with 100% JOB COMPLETED in VHDL/VERILOG. I am really suitable for job description: First: I am an Electronics engineer who is very expertise with VHDL/Verilog. In fact, I have done so many project of VHDL/Verilog(Karatsuba multiplier, Nintendo design, encryption algorithm like Sax Hash, Bernstein Hash, HummingBird...Also, I participated in a Walker Recognition project(data from Camera to Human Detection(image processing-HOG feature and Adaboost) and display in VGA). Besides,,I implemented the image conpression (wavelet transform). Aslo, I have experience in coding Booth multiplier and very familiar with Xilinx tools like ISE. and Vivado. Therefore, I can simulation the projecthe in behavior, post-syntheize... with free hesitation. I am also have experience of freelancer here: https://www.freelancer.com/u/ducdctoandh.html Also, I am very good in English (IELTS 6.0) and I have several year of researching so I can fully understand your requirement and understand fully about the papers and write the academic report. Please contact me and let me know if you want any special requirement and do with lower price. Thank you.
$30 USD en 1 día
4,9 (94 comentarios)
6,9
6,9
Avatar del usuario
A highly-skilled FPGA engineer with 6+ years experience and hundreds of FPGA/Verilog/VHDL projects using Xilinx/Altera FPGA Design Tools and Digital Logic Design using LogiSim/CEDAR. An FPGA/Verilog/VHDL Codementor and Founder of FPGA4student. Expertise: FPGA, Verilog, VHDL, Xilinx ISE, Vivado, Altera Quartus, Modelsim, Logisim, CEDAR, MIPS Assembly, Qtspim, MARS, PCB Design, Altium Designer, OrCAD, PSpice, Proteus, Arduino, VLSI/CMOS Design, Cadence ADE, /Virtuoso/Layout/Digital ASIC Design from RTL-GDSII. - Featured FPGA projects: + Video/Image Processing on FPGA: FPGA/Verilog/VHDL Implementation of Gesture Recognition, Fingerprint Identification, Image Compression in Wavelet Domain using DWT and SPIHT, Image Enhancements including Noise Filtering. + Fixed-point and Floating Point FPGA projects in Verilog/VHDL + AES, SHA 128, 192, 256 Implementations on FPGA + Single/Multicycle/Pipelined RISC/MIPS Processors in Verilog/VHDL/Logisim + Games on FPGA and many other projects
$25 USD en 1 día
4,9 (165 comentarios)
6,8
6,8
Avatar del usuario
Master in Engineering, Electrical and Electronic Engineer, who is dynamic, reliable, resourceful, committed and organized with enthusiastic approach to succeed with a pleasant attitude. Possessing excellent analytical skill and good research background. I have successfully completed IELTS with an overall band of 7 and have a good proficiency in English COMPLETED PROJECTS • FM radio. • VHDL Design of an Up/Down Counter. • Design of Up/Down Counter using PIC. • Duck Shooter Program using C. • Pointer movement controller on 2-dimentional axis using C. • LCD display Manipulation projects including: o Text Display o Volt-Meter • Analog to Digital Conversion (8-bit). • Sound to Light Color Organ Design and Development. • Minesweeper Player Creation using PIC. • Simulation of an End to End Communication System with MATLAB. • (BENG Individual Project) (MENG Part A). • (MENG Individual Project) (MENG Part B). • (MENG Group Project).
$25 USD en 1 día
4,7 (12 comentarios)
4,4
4,4

Sobre este cliente

Bandera de POLAND
Człuchów, Poland
5,0
1
Forma de pago verificada
Miembro desde ago 17, 2013

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