Fix Cadence XOR gate schematic

Cerrado Publicado hace 5 años Pagado a la entrega
Cerrado Pagado a la entrega

I have a very simple Cadence schematic and layout I have designed of an XOR gate. For some reason the nest lists do not match in the LVS check. I cannot figure out this simple task because I am new to the process.

The layout cannot change but corrections can be applied and the entire schematic can change to make the proper corrections to match the layout.

Diseño de circuitos Ingeniería eléctrica Electrónica Ingeniería Diseño PCB

Nº del proyecto: #18000481

Sobre el proyecto

7 propuestas Proyecto remoto Activo hace 5 años

7 freelancers están ofertando un promedio de $25 por este trabajo

loi09dt1

A highly-skilled FPGA engineer with 7+ years experience and hundreds of FPGA/Verilog/VHDL projects using Xilinx/Altera FPGA Design Tools and Digital Logic Design using LogiSim/CEDAR. Founder of FPGA4student. Expertise Más

$50 USD en 1 día
(126 comentarios)
6.7
prefectworld

Am full-time freelancer expert in Electrical & Electronic Circuit Designing & Simulation, PCB Designing, Consultancy of different types of Electrical & Electronic Problem. I can write Fix Cadence XOR gate schematic, I Más

$10 USD en 2 días
(23 comentarios)
5.1
rubelsarkar161

Hi, I am an IC Mask Layout Design Engineer. I can fix your problem in less than 1 hour. I have experience to design layout in TSMC/GF/XFAB/NCSU PDK @7/16/22/130/180nm node. I have Cadence Virtuoso also. I think yo Más

$20 USD en 1 día
(5 comentarios)
4.1
binarystar105

Hello, I've read your job description and I can help you with this task because I've 5+ years of experience using Cadence Virtuoso for all layers of VLSI design. I've faced this exact issue myself for there is a reaso Más

$35 USD en 1 día
(9 comentarios)
4.3
jasnaikaran

Hello, I am an electronics engineer having experience in design using cadence virtuoso for more than 5 years.

$10 USD en 1 día
(14 comentarios)
4.1
Wajeeha09

I can design this Relevant Skills and Experience I am electronic engineer , I can design xor gate for ypu

$25 USD en 1 día
(0 comentarios)
0.0