Build small educational Quartus project to illustrate Altera SDRAM IP usage in VHDL on FPGA

Board : Terasic DE10-Lite MAX10 10M50DAF484C7G - 2 push buttons - 10 switches - 6 7-segments - 1 SDRAM module (ISSI IS4216320D) - see [login to view URL] for more details about the board Software tool : Altera / Intel Quartus Prime Lite 16.1 Project : create a small, minimalistic, Quartus project to illustrate the use of PLL and SDRAM IP libraries. Description : 1) the user turns on or off each switch and defines a 10bit number 2) the user push the number into the SDRAM by pressing button #1 3) the user reads the numbers pushed into memory into the 7 segments by pressing button #2 Essentially that's it. Need well written, well documented, clean code.