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$25 USD / hora
Bandera de PAKISTAN
islamabad, pakistan
$25 USD / hora
Aquí son las 4:30 p. m.
Se unió el septiembre 11, 2015
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Bcube G.

@bcubeglobal

 0,0 (1 comentario)
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100%
$25 USD / hora
Bandera de PAKISTAN
islamabad, pakistan
$25 USD / hora
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DSP, FPGA, PCB,VHDL/Verilog, RF/MW

With over 30 years collective experience in electronics, We at Bcube Global strive for success of businesses and products. Masters in the field of High speed PCB design, FPGAs, verilog,VHDL and RF/MW circuit design, once chosen, We guarantee satisfaction at our end. Our team of engineers have worked on high speed PCBs stuffed with FPGAs, Processors, DDR2/3 interfaces, PHY chips and LVDS Signals all MANUALLY ROUTED. With IBIS models, We can SHOW you a PCB working on computer hence reducing risk of redesign. On FPGAs side, Our engineers have worked on most recent technologies like USB 3.0 Host IP core, DDR3 IP, 8051 IP and hybrid memory cube controller IP to name a few. We specialize in development of ultra-wide band RF/MW systems and sub-systems for wireless applications. We look forward to serve you professionally and up to your standards.
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Portafolio

2171118
High speed arbitrary signal generator capable of generating signals with frequency ranging from 10Hz to 200MHz. Ti\'s 1.5GSPS DAC3484 was used to generate analog outputs. Virtex-7 was used to generate input vectors for DAC3484. A Labview based GUI was also developed to provide user inputs, such as output frequency, amplitude, phase and sampling rate etc. These inputs were forwarded to the FPGA using USB-to-serial bridge. \n
Xilinx Virtex-7 (VC707) based signal generator
2171115
High speed communication platform utilizing Freescale PowerPC and Xilinx Virtex-2 FPGA. The platform was mainly designed as communication controller for remote sensing system. This platform provided RS-232, RS-422, SPI, I2C, NAND Flash, general purpose I/Os along with display, keypad, audio etc. interfaces. .
PowerPC + Virtex-2 based communication platform
High speed communication platform utilizing Freescale PowerPC and Xilinx Virtex-2 FPGA. The platform was mainly designed as communication controller for remote sensing system. This platform provided RS-232, RS-422, SPI, I2C, NAND Flash, general purpose I/Os along with display, keypad, audio etc. interfaces. .
PowerPC + Virtex-2 based communication platform
High speed communication platform utilizing Freescale PowerPC and Xilinx Virtex-2 FPGA. The platform was mainly designed as communication controller for remote sensing system. This platform provided RS-232, RS-422, SPI, I2C, NAND Flash, general purpose I/Os along with display, keypad, audio etc. interfaces. .
PowerPC + Virtex-2 based communication platform
2171096
We develop high speed, high density PCBs. Design complexity varies with PCBs having FPGAs, DSPs, RAMs with fine pitch BGA packages with single-ended and differential links operating at up to 9GBPS.
High speed PCB design
We develop high speed, high density PCBs. Design complexity varies with PCBs having FPGAs, DSPs, RAMs with fine pitch BGA packages with single-ended and differential links operating at up to 9GBPS.
High speed PCB design
We develop high speed, high density PCBs. Design complexity varies with PCBs having FPGAs, DSPs, RAMs with fine pitch BGA packages with single-ended and differential links operating at up to 9GBPS.
High speed PCB design
We develop high speed, high density PCBs. Design complexity varies with PCBs having FPGAs, DSPs, RAMs with fine pitch BGA packages with single-ended and differential links operating at up to 9GBPS.
High speed PCB design
2171088
Our work included developing MATLAB based instrumentation, algorithm development (image-processing), and simulations for 4G LTE uplink and downlink and graphical user interface (GUI) design.
MATLAB simulations and algorithm development
Our work included developing MATLAB based instrumentation, algorithm development (image-processing), and simulations for 4G LTE uplink and downlink and graphical user interface (GUI) design.
MATLAB simulations and algorithm development
Our work included developing MATLAB based instrumentation, algorithm development (image-processing), and simulations for 4G LTE uplink and downlink and graphical user interface (GUI) design.
MATLAB simulations and algorithm development
Our work included developing MATLAB based instrumentation, algorithm development (image-processing), and simulations for 4G LTE uplink and downlink and graphical user interface (GUI) design.
MATLAB simulations and algorithm development
2171084
A Systematic Technique for Hardware/Software Codesign Applied to Design of Sub-optimal MIMO Decoder. In this work we present a novel FPGA cost estimation technique to assist in design space exploration. Main strength of the technique is the ability to calculate area and speed estimates from higher level implementation such as MATLAB. This approach not only saves significant amount of time, but also provides the designer the opportunity to evaluate multiple algorithms from implementation perspective before actually starting the implementation phase. Our technique that makes use of pre-implemented libraries to develop fine estimates for different possible hardware architectures for a given algorithm. \nWhile our technique can be applied to any algorithm, we restrict ourselves to MIMO systems. We then implement this architecture using Xilinx Zynq-7000 device and compare actual results with the expected ones.
A Systematic Technique for Hardware/Software Codesign.
A Systematic Technique for Hardware/Software Codesign Applied to Design of Sub-optimal MIMO Decoder. In this work we present a novel FPGA cost estimation technique to assist in design space exploration. Main strength of the technique is the ability to calculate area and speed estimates from higher level implementation such as MATLAB. This approach not only saves significant amount of time, but also provides the designer the opportunity to evaluate multiple algorithms from implementation perspective before actually starting the implementation phase. Our technique that makes use of pre-implemented libraries to develop fine estimates for different possible hardware architectures for a given algorithm. \nWhile our technique can be applied to any algorithm, we restrict ourselves to MIMO systems. We then implement this architecture using Xilinx Zynq-7000 device and compare actual results with the expected ones.
A Systematic Technique for Hardware/Software Codesign.
A Systematic Technique for Hardware/Software Codesign Applied to Design of Sub-optimal MIMO Decoder. In this work we present a novel FPGA cost estimation technique to assist in design space exploration. Main strength of the technique is the ability to calculate area and speed estimates from higher level implementation such as MATLAB. This approach not only saves significant amount of time, but also provides the designer the opportunity to evaluate multiple algorithms from implementation perspective before actually starting the implementation phase. Our technique that makes use of pre-implemented libraries to develop fine estimates for different possible hardware architectures for a given algorithm. \nWhile our technique can be applied to any algorithm, we restrict ourselves to MIMO systems. We then implement this architecture using Xilinx Zynq-7000 device and compare actual results with the expected ones.
A Systematic Technique for Hardware/Software Codesign.
A Systematic Technique for Hardware/Software Codesign Applied to Design of Sub-optimal MIMO Decoder. In this work we present a novel FPGA cost estimation technique to assist in design space exploration. Main strength of the technique is the ability to calculate area and speed estimates from higher level implementation such as MATLAB. This approach not only saves significant amount of time, but also provides the designer the opportunity to evaluate multiple algorithms from implementation perspective before actually starting the implementation phase. Our technique that makes use of pre-implemented libraries to develop fine estimates for different possible hardware architectures for a given algorithm. \nWhile our technique can be applied to any algorithm, we restrict ourselves to MIMO systems. We then implement this architecture using Xilinx Zynq-7000 device and compare actual results with the expected ones.
A Systematic Technique for Hardware/Software Codesign.
A Systematic Technique for Hardware/Software Codesign Applied to Design of Sub-optimal MIMO Decoder. In this work we present a novel FPGA cost estimation technique to assist in design space exploration. Main strength of the technique is the ability to calculate area and speed estimates from higher level implementation such as MATLAB. This approach not only saves significant amount of time, but also provides the designer the opportunity to evaluate multiple algorithms from implementation perspective before actually starting the implementation phase. Our technique that makes use of pre-implemented libraries to develop fine estimates for different possible hardware architectures for a given algorithm. \nWhile our technique can be applied to any algorithm, we restrict ourselves to MIMO systems. We then implement this architecture using Xilinx Zynq-7000 device and compare actual results with the expected ones.
A Systematic Technique for Hardware/Software Codesign.
A Systematic Technique for Hardware/Software Codesign Applied to Design of Sub-optimal MIMO Decoder. In this work we present a novel FPGA cost estimation technique to assist in design space exploration. Main strength of the technique is the ability to calculate area and speed estimates from higher level implementation such as MATLAB. This approach not only saves significant amount of time, but also provides the designer the opportunity to evaluate multiple algorithms from implementation perspective before actually starting the implementation phase. Our technique that makes use of pre-implemented libraries to develop fine estimates for different possible hardware architectures for a given algorithm. \nWhile our technique can be applied to any algorithm, we restrict ourselves to MIMO systems. We then implement this architecture using Xilinx Zynq-7000 device and compare actual results with the expected ones.
A Systematic Technique for Hardware/Software Codesign.
2171080
We design RF/MW circuits and PCBs. We have design capabilities of passive circuits including filters, power dividers, multiplexers, couplers etc. and active circuits like Low noise amplifiers, High power amplifiers, oscillators, mixers etc.\n\nWe design and layout custom high frequency PCBs for different ICs (LP, LC, QFN etc packages) including evaluation boards. We also design complete RF/MW systems including transmitters, receivers, up/down converters, local oscillators etc. \n\nWe also provide fabrication and testing services for circuits up to 20 GHz.
RF/Microwave circuits and systems
We design RF/MW circuits and PCBs. We have design capabilities of passive circuits including filters, power dividers, multiplexers, couplers etc. and active circuits like Low noise amplifiers, High power amplifiers, oscillators, mixers etc.\n\nWe design and layout custom high frequency PCBs for different ICs (LP, LC, QFN etc packages) including evaluation boards. We also design complete RF/MW systems including transmitters, receivers, up/down converters, local oscillators etc. \n\nWe also provide fabrication and testing services for circuits up to 20 GHz.
RF/Microwave circuits and systems
We design RF/MW circuits and PCBs. We have design capabilities of passive circuits including filters, power dividers, multiplexers, couplers etc. and active circuits like Low noise amplifiers, High power amplifiers, oscillators, mixers etc.\n\nWe design and layout custom high frequency PCBs for different ICs (LP, LC, QFN etc packages) including evaluation boards. We also design complete RF/MW systems including transmitters, receivers, up/down converters, local oscillators etc. \n\nWe also provide fabrication and testing services for circuits up to 20 GHz.
RF/Microwave circuits and systems
2171118
High speed arbitrary signal generator capable of generating signals with frequency ranging from 10Hz to 200MHz. Ti\'s 1.5GSPS DAC3484 was used to generate analog outputs. Virtex-7 was used to generate input vectors for DAC3484. A Labview based GUI was also developed to provide user inputs, such as output frequency, amplitude, phase and sampling rate etc. These inputs were forwarded to the FPGA using USB-to-serial bridge. \n
Xilinx Virtex-7 (VC707) based signal generator
2171115
High speed communication platform utilizing Freescale PowerPC and Xilinx Virtex-2 FPGA. The platform was mainly designed as communication controller for remote sensing system. This platform provided RS-232, RS-422, SPI, I2C, NAND Flash, general purpose I/Os along with display, keypad, audio etc. interfaces. .
PowerPC + Virtex-2 based communication platform
High speed communication platform utilizing Freescale PowerPC and Xilinx Virtex-2 FPGA. The platform was mainly designed as communication controller for remote sensing system. This platform provided RS-232, RS-422, SPI, I2C, NAND Flash, general purpose I/Os along with display, keypad, audio etc. interfaces. .
PowerPC + Virtex-2 based communication platform
High speed communication platform utilizing Freescale PowerPC and Xilinx Virtex-2 FPGA. The platform was mainly designed as communication controller for remote sensing system. This platform provided RS-232, RS-422, SPI, I2C, NAND Flash, general purpose I/Os along with display, keypad, audio etc. interfaces. .
PowerPC + Virtex-2 based communication platform
2171096
We develop high speed, high density PCBs. Design complexity varies with PCBs having FPGAs, DSPs, RAMs with fine pitch BGA packages with single-ended and differential links operating at up to 9GBPS.
High speed PCB design
We develop high speed, high density PCBs. Design complexity varies with PCBs having FPGAs, DSPs, RAMs with fine pitch BGA packages with single-ended and differential links operating at up to 9GBPS.
High speed PCB design
We develop high speed, high density PCBs. Design complexity varies with PCBs having FPGAs, DSPs, RAMs with fine pitch BGA packages with single-ended and differential links operating at up to 9GBPS.
High speed PCB design
We develop high speed, high density PCBs. Design complexity varies with PCBs having FPGAs, DSPs, RAMs with fine pitch BGA packages with single-ended and differential links operating at up to 9GBPS.
High speed PCB design
2171088
Our work included developing MATLAB based instrumentation, algorithm development (image-processing), and simulations for 4G LTE uplink and downlink and graphical user interface (GUI) design.
MATLAB simulations and algorithm development
Our work included developing MATLAB based instrumentation, algorithm development (image-processing), and simulations for 4G LTE uplink and downlink and graphical user interface (GUI) design.
MATLAB simulations and algorithm development
Our work included developing MATLAB based instrumentation, algorithm development (image-processing), and simulations for 4G LTE uplink and downlink and graphical user interface (GUI) design.
MATLAB simulations and algorithm development
Our work included developing MATLAB based instrumentation, algorithm development (image-processing), and simulations for 4G LTE uplink and downlink and graphical user interface (GUI) design.
MATLAB simulations and algorithm development
2171084
A Systematic Technique for Hardware/Software Codesign Applied to Design of Sub-optimal MIMO Decoder. In this work we present a novel FPGA cost estimation technique to assist in design space exploration. Main strength of the technique is the ability to calculate area and speed estimates from higher level implementation such as MATLAB. This approach not only saves significant amount of time, but also provides the designer the opportunity to evaluate multiple algorithms from implementation perspective before actually starting the implementation phase. Our technique that makes use of pre-implemented libraries to develop fine estimates for different possible hardware architectures for a given algorithm. \nWhile our technique can be applied to any algorithm, we restrict ourselves to MIMO systems. We then implement this architecture using Xilinx Zynq-7000 device and compare actual results with the expected ones.
A Systematic Technique for Hardware/Software Codesign.
A Systematic Technique for Hardware/Software Codesign Applied to Design of Sub-optimal MIMO Decoder. In this work we present a novel FPGA cost estimation technique to assist in design space exploration. Main strength of the technique is the ability to calculate area and speed estimates from higher level implementation such as MATLAB. This approach not only saves significant amount of time, but also provides the designer the opportunity to evaluate multiple algorithms from implementation perspective before actually starting the implementation phase. Our technique that makes use of pre-implemented libraries to develop fine estimates for different possible hardware architectures for a given algorithm. \nWhile our technique can be applied to any algorithm, we restrict ourselves to MIMO systems. We then implement this architecture using Xilinx Zynq-7000 device and compare actual results with the expected ones.
A Systematic Technique for Hardware/Software Codesign.
A Systematic Technique for Hardware/Software Codesign Applied to Design of Sub-optimal MIMO Decoder. In this work we present a novel FPGA cost estimation technique to assist in design space exploration. Main strength of the technique is the ability to calculate area and speed estimates from higher level implementation such as MATLAB. This approach not only saves significant amount of time, but also provides the designer the opportunity to evaluate multiple algorithms from implementation perspective before actually starting the implementation phase. Our technique that makes use of pre-implemented libraries to develop fine estimates for different possible hardware architectures for a given algorithm. \nWhile our technique can be applied to any algorithm, we restrict ourselves to MIMO systems. We then implement this architecture using Xilinx Zynq-7000 device and compare actual results with the expected ones.
A Systematic Technique for Hardware/Software Codesign.
A Systematic Technique for Hardware/Software Codesign Applied to Design of Sub-optimal MIMO Decoder. In this work we present a novel FPGA cost estimation technique to assist in design space exploration. Main strength of the technique is the ability to calculate area and speed estimates from higher level implementation such as MATLAB. This approach not only saves significant amount of time, but also provides the designer the opportunity to evaluate multiple algorithms from implementation perspective before actually starting the implementation phase. Our technique that makes use of pre-implemented libraries to develop fine estimates for different possible hardware architectures for a given algorithm. \nWhile our technique can be applied to any algorithm, we restrict ourselves to MIMO systems. We then implement this architecture using Xilinx Zynq-7000 device and compare actual results with the expected ones.
A Systematic Technique for Hardware/Software Codesign.
A Systematic Technique for Hardware/Software Codesign Applied to Design of Sub-optimal MIMO Decoder. In this work we present a novel FPGA cost estimation technique to assist in design space exploration. Main strength of the technique is the ability to calculate area and speed estimates from higher level implementation such as MATLAB. This approach not only saves significant amount of time, but also provides the designer the opportunity to evaluate multiple algorithms from implementation perspective before actually starting the implementation phase. Our technique that makes use of pre-implemented libraries to develop fine estimates for different possible hardware architectures for a given algorithm. \nWhile our technique can be applied to any algorithm, we restrict ourselves to MIMO systems. We then implement this architecture using Xilinx Zynq-7000 device and compare actual results with the expected ones.
A Systematic Technique for Hardware/Software Codesign.
A Systematic Technique for Hardware/Software Codesign Applied to Design of Sub-optimal MIMO Decoder. In this work we present a novel FPGA cost estimation technique to assist in design space exploration. Main strength of the technique is the ability to calculate area and speed estimates from higher level implementation such as MATLAB. This approach not only saves significant amount of time, but also provides the designer the opportunity to evaluate multiple algorithms from implementation perspective before actually starting the implementation phase. Our technique that makes use of pre-implemented libraries to develop fine estimates for different possible hardware architectures for a given algorithm. \nWhile our technique can be applied to any algorithm, we restrict ourselves to MIMO systems. We then implement this architecture using Xilinx Zynq-7000 device and compare actual results with the expected ones.
A Systematic Technique for Hardware/Software Codesign.
2171080
We design RF/MW circuits and PCBs. We have design capabilities of passive circuits including filters, power dividers, multiplexers, couplers etc. and active circuits like Low noise amplifiers, High power amplifiers, oscillators, mixers etc.\n\nWe design and layout custom high frequency PCBs for different ICs (LP, LC, QFN etc packages) including evaluation boards. We also design complete RF/MW systems including transmitters, receivers, up/down converters, local oscillators etc. \n\nWe also provide fabrication and testing services for circuits up to 20 GHz.
RF/Microwave circuits and systems
We design RF/MW circuits and PCBs. We have design capabilities of passive circuits including filters, power dividers, multiplexers, couplers etc. and active circuits like Low noise amplifiers, High power amplifiers, oscillators, mixers etc.\n\nWe design and layout custom high frequency PCBs for different ICs (LP, LC, QFN etc packages) including evaluation boards. We also design complete RF/MW systems including transmitters, receivers, up/down converters, local oscillators etc. \n\nWe also provide fabrication and testing services for circuits up to 20 GHz.
RF/Microwave circuits and systems
We design RF/MW circuits and PCBs. We have design capabilities of passive circuits including filters, power dividers, multiplexers, couplers etc. and active circuits like Low noise amplifiers, High power amplifiers, oscillators, mixers etc.\n\nWe design and layout custom high frequency PCBs for different ICs (LP, LC, QFN etc packages) including evaluation boards. We also design complete RF/MW systems including transmitters, receivers, up/down converters, local oscillators etc. \n\nWe also provide fabrication and testing services for circuits up to 20 GHz.
RF/Microwave circuits and systems

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₹200.000,00 INR
Linescan CCD camera system development
Ata (bcubeglobal) was not able to complete the project even after having given complete support and details. Stay away.
C Programming
Electronics
C# Programming
Microcontroller
PCB Layout
Avatar del usuario
Bandera de Akshay J.
@Microconprojects
•
hace 8 años

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Principales habilidades

C Programming
Wireless
Electronics
Matlab and Mathematica
Verilog / VHDL

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