Scrypt fpgatrabajos
... This project is for a team of VHDL expert and Java expert. I have a dev. FPGA board embedded the chip AD9764. This is the DAC. I already have a complete project written in vhdl including other modules apart of this project. I need you to simulate and fix the data transmission part between the client application to the DAC AD9764, which is a 14-bit output resolution DAC. FPGA is a Xilinx XC3S500E. I need you to change VHDL of the DAC controller, and to change the I need you to change the client application written in Java, using the chosen protocol through UART. The client app should be able to generate and emit signal(waveform) through UART. You have worked with signal acquisition and processing in FPGA with high speed ADC and DAC. You know VHDL coding. You alr...
Have a coin based on the algorithm SCRYPT. I need this made asic proof because these machines are destroying the mining network. Please post that you are aware that it is the SCRYPT ALGO and you can complete this project. PLEASE GIVE ME A BRIEF IDEA OF HOW YOU WILL ACCOMPLISH THE PROJECT. Thank you.
I have a cryptocurrency coin that runs on the Scrypt Algorithm. ASIC miners have destroyed the mining network and changes need to be made to help slow this down or prevent this going forward. I need to hire someone to do this for me. Please list a price and how you will accomplish this. Thank you for looking.
...para os usuários. Desenvolver um Website para Exchange, para que possamos fazer as comercializações dessa cryptocurrency, Bitcoin ou outras cryptocurrencys. Posso auxiliar no processo do desenvolvimento de Logo, Whitepaper, e afins. Tenho um estudo que seria uma moeda ideal com o melhor custo benefício para o meu público de atuação e utilização dessa moeda. Dados técnicos: Algorithm: Scrypt Type: PoW Coin name: (confidencial) Coin abbreviation: (Confidencial) Address letter: U RPC port: 32016 P2P port: 32015 Block reward: 200 coins Block halving: 840000 blocks Coin supply: 346391753 coins Advanced properties Coinbase maturity: 20 blocks Target spacing: 5 minutes Target timespan: 10 m...
A very simple oscilloscope developed using Verilog on Altera software, this project will be based on DE1-SoC Board and is expected to be concluded within a week. Only experienced FPGA engineers please.
So the what I need to do is fairly easy, However I am new in using Vivado...Project. It will be controlled by an Android App. However my part of the project is the FPGA. I need to create a block design in vivado. I am using the ZYNQ7 processing system for my IP. I need to have the BRAM and DAC in the design and also other components which i'm not sure which ones. I have been searching online for help but can't find anything. the blocks need to be connected how the system should work. I am working with the picozed 7010. I will attach pictures of my parts and also the DAC data sheet I am using. I attached also a description of how my project should be. It is named FULLTEXT. Its an example project. I also attached pictures of the boards I'm using. They are 2 boards picoz...
Hey, We want a wordpress payment plugin for our own cryptocurrency which is on Scrypt Hybrid Algorithm. Only the people with blockchain and cryptocurrency experience can bid
Hello I am looking for some to build and cusotmize the opencl FPGA based on AMD etc. Especially you have rich experience with FPGA network communication.. Please send me message if you are ready with this project.
Fork form Litecoin (Laste Version) Block-chain = Public Block-chain Consensus = Proof of Work (POW) Algorithm = Scrypt Total Coin Supply= 50000000 Block Time = 35 Seconds Block Size = 8MB Decimal= 8 digits Pre-mined= 10000000 Mining= Yes Explorer= Yes Wallet = Windows, Mac Support to join Exchange Market = Yobit or Market Cap
I need someone to help me modify a Demo(FPGA: Xilinx Basys3 Language:Verilog) which is a object tracking system based on a pan-tilt. I think the modification won't be a big task, because the imaging processing algorithm works well, the need of modification is in controling two servos, especilly in getting back servos' position. The original demo get servos' position by using four wires servo(PWM Vcc GND feedback). But I cannot find this kind of servo in the online shops. Actually, I have some plans. a. writing an algorithm like this blog, b. using some sensors like Accelerometer Magnetometer Gyroscope. But I think there might be several problems. For accelerometer and gyroscope. Integral will increase
Board : Terasic DE10-Lite MAX10 10M50DAF484C7G - 2 push buttons - 10 switches - 6 7-segments - 1 SDRAM module (ISSI IS4216320D) - see for more details about the board Software tool : Altera / Intel Quartus Prime Lite 16.1 Project : create a small, minimalistic, Quartus project to illustrate the use of PLL and SDRAM IP libraries. Description : 1) the user turns on or off each switch and defines a 10bit number 2) the user push the number into the SDRAM by pressing button #1 3) the user reads the numbers pushed into memory into the 7 segments by pressing button #2 Essentially that's it. Need well written, well documented, clean code.
This project aims at conceiving GNU-Radio blocs for receiving / transmitting modulated radio messages using Software Defined Radio (SDR). I need a software component lib called "gr-beaglesdr" of a software-defined radio receiver and ...transmitter combined with suitable hardware device BeagleSDR. It can be used to listen to or display data from a variety of radio transmissions and also send waveform. "gr-beaglesdr" should support most of common features like CRC checks of the payload and header, decoding channel in real time... This library will primarily be tested with BeagleSDR as receiver and as transmitter. There are both AVR, FPGA, SDRAM, ADC and DAC inside BeagleSDR. You would be provided a sample of BeagleSDR board, however you need Beagleboard-x15 to ...
://%252091.pdf&ved=2ahUKEwjKmeiMk8faAhVFMY8KHd8qCEEQFjAAegQIBhAB&usg=AOvVaw1WcUfpr6ABVGsjjr8prZwM The link of the paper from which you have to make the project is attached. This paper consists the method you will have to use to implement the project. Everything is mentioned clearly in it. I want this project before Saturday morning. So the final system should detect faces present in an image implement ed using system generator.
Tcp sending on FPGA using verilog xgmii xilinx vivado
This is an FPGA/Verilog project to send some TCP packets over 10g SFP+ network to a tcp server.
I need you to develop some software for me. I would like this software to be developed . You will have to program an FPGA card that I will provide, to work for crypto mining. I will provide the software that works under windows and Linux and you will have to make this software works with the FPGA that will provide to you. Software will have to be perfectly optimized. You will work in our offices in our country in Europe. We'll provide food and accommodation. This could also be your chance to obtain a residential permit in our country in Europe. You will be hired with a regular working contract and nit disclosure contract. You will be working under supervision. Deadline to complete the programming is 30 to 45 days. So you MUST be expert at programming FPGAs. Y...
Android development of app client to send (internet) sound and inertial sampling Hardware design of server (FPGA/SoC) to compute RT responses of precise positioning and navigation, taking into account multipath, doppler effect by movement, .. Also desiderable "roaming" to GPS coordinates to map position
I am looking for someone to modify the OpenCL code base of an AMD focused Crypto Mining Software and optimize it for OpenCL Based FPGA using this package Please respond directly with any questions such as specific mining software and such.
Help me to research and find a suitable FPGA board for my project.
I have a scrypt based coin i need to add the masternode feature in the already POS and POW coin. Changes needs to be added in the windows wallet and Linux wallet also. Along with the tutorial in setting up the MN. Only verified candidate apply for this job with experience in Masternodes.
I want to get a simple 3 layer (Input-Hidden-Output) layer neural network implemented on an FPGA. The network I wish to implement is a wide network with hidden neurons ~1000-2000. I want this to be implemented for highest data throughput with optimized resource utilization. Also want to software to be written for the implemented hardware.
Details later.. I will check your BASIC.. And then recruit You
Program a FPGA to work as a MC6803 on a device like a Digilent Cmod A7: Breadboardable Artix-7 FPGA Module. . will need relevant information to program multiple devices.
I need help to clear the error in verilog code to make the fpga work. > Modules are already created with 2 feature of audio effects (delay and musical instrument) >Need help to clear the error, edit the code and make it work in fpga > Only 1 bitstream can be generated
Block-chain: Public Block-chain Consensus: Proof of Work (POW) Algorithm : Scrypt Total Coin Supply: 50,000,000 Block Time: 59 Seconds Block Size: 8MB Decimal: 8 digits Pre-mined: 10,00,000 Mining Pool: Yes Explorer: Yes Wallet Windows, Mac, Linux API Coin Market Cap, Exchange and Merchant
Hi guys, I'm facing a strange problem with a design. The design is very simple: I send 31 bytes from my computer to the FPGA (through UART), the FPGA makes some calculations and then I receive 54 bytes back to my PC (through UART again). The problem is that, I'm not receiving what is expected according to the simulation. Moreover, everytime I send the same bytes to the FPGA, I get back a different answer (which is not possible). I was thinking in a metastability in the UART, so I made a test removing the calcution module, making a design just with the UART itself, and the UART worked perfectly. In addition, I added two D flip flops at the input port to avoid any possible problem related to metastability, but the problems persists. So, I need someone who can...
...without a significant re-design of the boards themselves. Ideally, the successful candidate would also be able to re-write the FPGA firmware to accommodate a faster ADC chip. We are currently using an 80 MSPS 14 bit ADC (AD9245BCPZ-80), which is the fastest in that specific form factor. Ideally, we would like to go as high as 180 MSPS whilst keeping the board the same size. This would require some re-work of the board and a re-writing of the FPGA code. We do have a design for a modern Rx board, but have no firmware for this new board as yet. One option would be to either create a hybrid Rx board, or write new firmware for the new board based on the original board’s FPGA code....
The task is to implement one direction data flow from FPGA to PC using: 1. Evaluation board Terasic DE0-CV () and 2. wiz830mj (). The data should be sent to PC by TCP/IP protocol. The correct solution implies Verilog source code, which initializes W5300 chip and sends some data to PC by TCP/IP. The solution should be verified by sending ascending numbers from 0 to 255(8 bits) in an endless cycle. Providing a testing program (recieving data on PC side) with C++ source should be considered as an advantage.
Block-chain: Public Block-chain Consensus: Proof of Work (POW) Algorithm : Scrypt Total Coin Supply: 50,000,000 Block Time: 59 Seconds Block Size: 8MB Decimal: 8 digits Pre-mined: 10,00,000 Mining Pool: Yes Explorer: Yes Wallet Windows, Mac, Linux API Coin Market Cap, Exchange and Merchant
我公司有一个项目， cy7c68013A_128 单片机的软件开发， 细节是用GPIO模仿Jtag烧录两片Xilinx的PROM. (XCF04S, XCF01S). Xilin有比较详细的方案。 见副件。 如果你们承接这类工程， 请你给我一个报价。 我们有硬件平台， 你们需要提供， 1 windows usb 的驱动， 指定等待下载的文件。 Cy7c68013A 的程序，把指定的文件烧录到目标PROM. 启动系统， 读取FPGA内部寄存器，确定烧录成功。
I am looking for someone that can program or port an existing Windows or Linux mining program for AMD GPU's to a Xilinx Kintex-7 FPGA I will provide details and Github privately
I am looking for someone who is familiar with and have access to the following Electronic systems/subjects: - Op-Amps - Multisim - FPGA/Quartus PRime - Mbed Microcontrollers - Digital Analogue converters (DAC) - using R-2R Ladder If you do not have relevant skills and access please do not apply Thank you
I want to build Litecoin Base coin in with Scrypt algorithm with windows, Linux, web, Android and iOS wallet. Further details will.
To create a real time audio effects machine using FPGA. It includes the following: 1.Real-time microphone-speaker system (capture voice from them PmodMIC3 and output at PmodAMP2). 2.Real-time delay in microphone-speaker system. Music Instrument. integration. extra feature (open-ended). Verilog code will be given and it can edit according to the project.
its in a document that ill share with you once we discuss .
Create a real time audio effects machine. provided with a MEMs microphone to capture human voice and an audio amplifier to output your signal through earphones. This manual introduces you to the various concepts involved, and guides (not walks!) you through getting an audio FX machine up and running. Details given below
is the website is a typical review page format We review a range of different products, so don't just focus on bitcoin. We'll need the logo in a vector type format Needs to be clean, modern, looks good when scaled big or small NO GRADIENTS current logo: rejected logos:
Hi Vijayvithal J., I noticed your profile and I am considering offering you my FPGA project. Off the bat I would like to offer you 50$ for an hour of your time to develop a plan and budget for this work. We can discuss further details over chat after you have reviewed my specification document. I hope this project sounds interesting to you and I am able to send the required hardware to you if we decide to go forward.
Por favor, regístrate o inicia sesión para ver los detalles.
...eine Infografik welche in etwa das gleiche darstellen soll wie die Grafik "Beispiel 1". Natürlich soll die Grafik keine Kopie werden, sondern individuell Designed werden und dafür brauche ich die Hilfe und Kreativität eines Freelancer. In der Grafik soll der "Bitpower" (unser Produkt) bildlich veranschaulicht werden. Der Bitpower setzt sich zusammen aus ... - GPU Altcoin (Scrypt-N, Equihash) - ASIC Altcoin (Scrypt, X11, X13, X14, X15) - ASIC Bitcoin & Bitcoin Cash (SHA-256) ...dies sind auch die Daten welche in der Grafik beschrieben werden soll. Diese verschiedenen Technologien nutzen wir. In dem Bitpower ist ebenso Einkauf, Optimierung , Installation und Betrieb mit inbegriffen - es wäre toll, wenn man dies ebenso in ...
Error Correction Blocks Configuration (Viterbi+Reed Solomon) on an ARTIX7-200T FPGA supporting 200 Mbps is needed. The bidder must use open source or free Viterbi decoders-Reed Solomon en/decoders-(De)Interleavers-Pseudorandom number generators (PRBS). The Viterbi Decoder must be parameterizable (K=7, 1/2,3/4,7/8 puncturing etc.) and must support soft decision. The Reed Solomon En/Decoder must be set to (223,255) The Interleaver must be parameterizable A Framer/Deframer must add/ remove Headers into the bitstream and should indicate a lock. The Transmit Chain: Data Source(PRBS)-> RS Encoder->Framer->Convolutional Coder- The Receive Chain: Viterbi decoder(soft decoding)->Deframer and Lock detection->RS decoding->PRBS Lock detection and BER Measurem...
...well known project for running pools to mine crypto currency. We want to update the current project, deploy to VMWare ESXi, document all steps and verify. The goal will be to publish the work for free download. Algorithms Native - SHA256d, scrypt, scryptn or x11 NOMP - scrypt", //or "sha256", "scrypt-jane", "scrypt-n", "quark", "x11"() CoiniumServ - Scrypt, SHA256d, X11, X13, X14, X15, X17, Blake, Fresh, Fugue, Groestl, Keccak, NIST5, Scrypt-OG, Scrypt-N, SHA1, SHAvite3, Skein, Qubit () 1. Start with existing MPOS project - https://www.freelancer.com/projects/linux/open-source-crypto-currency-miner/ 2. Deploy to VMWare ESXi or other
...freelancer.com/projects/linux/Open-Source-Crypto-Currency-Miner/ "CoiniumServ" is a well known project for running pools to mine crypto currency. We want to update the current project, deploy to VMWare ESXi, document all steps and verify. The goal will be to publish the work for free download. Algorithms Scrypt, SHA256d, X11, X13, X14, X15, X17, Blake, Fresh, Fugue, Groestl, Keccak, NIST5, Scrypt-OG, Scrypt-N, SHA1, SHAvite3, Skein, Qubit 1. Start with existing CoiniumServ project - https://www.freelancer.com/projects/linux/Open-Source-Crypto-Currency-Miner/ 2. Deploy to VMWare ESXi or other virtualization platform 3. Deploy http and stratum miner support for 19 listed algorithms. 4. Basic requirements: - VMWare ESXi - Ubuntu 16.04 - My...
A (PSK) modulator/ demodulator for the ARTIX7-200 platform is needed. This project is a mere test for the abilities of the bidder. Several Add-On projects will follow. An PSK (BPSK, QPSK, OQPSK, 8-PSK) modulator/ demodulator for the ARTIX7-200 platform is needed. The PSK modulator must have a sampling rate selection between 1ksps-400 MSPS, The PSK demodulator must have a sampling rate selection between 1ksps-200 MSPS,(100 MSPS for BPSK) The developer will develop a PSK (BPSK, QPSK,OQPSK,8-PSK) modulator/ demodulator core . The demodulator core must perform all the carrier and clock recovery mechanisms (costas loop etc.) The PSK modulator will be generate 12 bit I&Q signals and will feed the signals to the demodulator. The Input to the modulator should be a PRBS sequence....
We are in need of an experienced developer to help us modify existing drivers based on Java to communicate with a FPGA based Bill validator from a Raspberry pi over USB. We previously modified existing java files to communicate with a bill validator that we later found out was using an old PSD based chip, whereas the new devices are based on FPGA chips. Our old code does not communicate with these newer devices and we need help modifying the drivers to enable them to communicate. We are using a raspberry pi (raspian) to control the device. Existing Java drivers for RedHat exist and may be useful to modify for the raspberry. I have included the below files that may be useful in completing this project. Linux : These are the existing ReHat drivers MEI_LINUX_API_REDHAT...
We are developing FPGA using Amazon AWS F1 service. The source code was converted from systemc to verilog using Vivado HLS. Many FPGA tool related issues needs to have an expert to help us. Including: 1) FPGA timing closure constraint 2) Place & route issues. 3) Set up clock divider to CL logic. Potentially, we have a lot more work if you are familiar with Vivado HLS, and systemc. Thanks
Altcoin already developed and launched,with source code which can compile qt wallets and ,the mining algorithm (scrypt) is wrongly chosen and a few ASIC miners quickly dominate the mining and make all other GPU miners unable to to change the algorithm to a ASIC resistant one (e.g. Equihash,Timetravel 10 or something suggested by programmer ).Moreover,change the blocksize to 8 Mb and other parameters remain give me back the amended source code with compiled qt wallets(windows, linux, osx) and linux turnaround. Because the coins already cannot be a "start over" just make the few amendments and I release the new version of qt wallets and daemon to the users and they can use the coins they already had. The quote price
