I'm computer engineer and hardware lecturer with 15+ years of experience.
I'm experienced with computer architecture , microprocessors , modelsim , VHDL
control unit design , RTL , micro-operations , 80x86 based architectures and their assembly language design and programming
experienced implementing many mega projects using FPGAs using verilog/system verilog/VHDL
including complete 2G/3G transceiver , encryption of the AES/DES/KASUMI/SAFER+
experienced working with spartan 3, spartan6, zynq [zybo and zc-702 kit]